Sharp CE-158 Manual do Utilizador descarregar pdf (Página 16)

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5 PERIPHERAL STATUS

TERRUPT (PSI):

This

bit

se t high by a

high·t<>-lo

w voltage transition

Term

(PSI

The INTERRUPT

out

put

(Term. 13) is also asserted ( INT = low)

whe

n this bit

set.

TRANSMITTER SHI

REGI

ER E

MPTY

(TSRE):

en set high, this bit indicates that the Transmitter Shift Register has completed ser

l trans·

mission

of a

character including st

bit(s).

remains sci until the start or trans

ssion o f

e next cha

cter.

7 TRANSMITT

HOLDING R

ISTER EMPTY (THRE):

en set high, this bi t indicates that the Transmitt

Hol ding Register has transferred its

contents to

the

Transmitter

ift Register and may be reloaded

th a new character. Setting this

bit

also sets t

THRE

output

(Term. 22) low

and

causes an INTERRUPT (I

NT=

low),

TR is

high.

4. Peripheral Interface

In addition

serial data in and o ut, fo

signals arc provided for communication with a peripheral.

n ie REQUEST TO SET

(RTS) o

utput

sign

al al

e periphe

l to

l ready 10 recei

The

CLEAR TO SE

(CTS)

inpu

t sign

the response, signalling that the peripheral is ready. The

EXTERNAL STATUS (ES) input latches a peripheral Slatus level, and

the

PERIPHERAL STATUS

TER

RUPT

SI) input

senSC$

a status edge (high·lo·low)

and

also generates an interrupt. Fo r

example, the modern DATA

R DETECT line could be connected

the

l'sfinpu

ART

in ord

microprocessor

at t

nsmission failed because of loss

the

carri

on the commu

cations lin

The PSI and ES bits arc stored in the Sta tus Regist

(See Fi

4 ).

1oc•

so1

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TPS

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•

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;

!--

• C

ICP~

:----:

···

---------------------

-.;,....;_

1'C

,.....-.

Ft;I

- -

-------

---

-----

-=-

-'--

Fig. 5 - MODE I receiver timing diagram.

' I

BIT

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TIME

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