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ll

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C-

1500 at http://www.PC-1500.info

3. Receiver Operation

The

receive

operation begins when a start bit is detected

at

the SERIAL

DA

TA

IN

(SDI) input.

After detection

of

the first

high

·to-low t

ra

nsition on the

SDI

line, a valid start bit is verified by

check

ing

for a

low

-l

ave!

input

7-1/2

receiver clock

peri<>ds

later.

When

a

vaUd

start bit

has

been

verified, the following data bits, parity bit

(if

programmed) and stop bit(s) are shifted into the

Receiver Shift Register by clock pulse

7-1/2 in each bit time. The parity

bit

(if programmed) is

checked and

receipt

of

a valid stop bit

is

verified. On count 7

-1

/2

of

the first stop bit, the

received

data

is

l

oa

ded

into

the

Rec

eiver Holding

Regis1er

. If the word length

is

l

ess

than 8 bits, zeros (low

output

le

ve

l) a

rc

loaded into the unused most significant bits. If

DATA

AVAILABLE

(DA) has not

been reset by

tbe time the Receiver Holding Register

is

loaded, the

OVERRUN

ERROR (OE) status

bit

is

set. One half clock period later, the PARITY ERROR

(PE.)

and

FRAMING

ERROR (FE)

status bits become valid

for

the character

in

the Rec

ei

ver

Holding Register. At this time, the Data

Available status bit is also set and the Data

Avai]able

status bit

is

also set and the

DATA

AVAILABLE

(DA) and INTERRUPT (INT) outputs

go

low, signalli

ng

the microprocessor that a

received charac.ter is ready. The

mic

roprocessor

res

p

ond.<

by executing an input instruction. The

UART's 3-state bus drivers

are

enabled when the UART

is

selected (

CS!

·

CS2

·

CS3

= I) and

RD/WR

= high. Status

can

be

re

ad

when

RS

EL =high. Data is read

when

RSE

L =

Low

. When read-

ing

data,

TPB

lat

ches data

in

the microprocessor and resets

DAT

A

AV

Al

LAB

LE

(DA) in the

UAR

T.

The preceding sequence

is

repeated

fo

r each serial character

which

is

received from the peripheral.

STATUS REGISTER

BIT

ASSIGNMENT

TABLE

Bit

7 6 5

4

3

2 I 0

Signal

THRE TSRE

PSI

ES

FE

PE

OE

DA

Also

Availa

ble

22•

14

15

15

19•

at Te

rminal

•P

olar

ity

r

eversed

at

o

ut

put te

rminal

,

Fig.

4 - Status Re

gi

ster bit assignment

BIT

SIGNAL:

FUNCTION

0 DATAAVAlLABLE(DA):

When

set high, this bit indicat

es

that an entire character

has

been

received

and

tr

ansferred

to

the

Rec

ei

ver

Holding

Registe

r.

11\is

signal

is

also available at

Tem1

.

19

but with its polarity

reversed

.

OVERRUN

ERROR (OE):

When

se

t hi

gh,

this bit indicates that the Data Available bit

was

not reset before the next

character

w"'

transferred

to

the Receiver Holding Register. This

signal

OR

'ed with

PE

is output

at

Term

. 15.

2

PARITY

ERROR (PE):

When

set h

igh

, this

bit

in

d

icat

es

that the received parity bit docs not compare to that

pro-

grammed by the

EVEN

PARITY

ENABLE

(

EPE)

contro

l.

This bit is updated each

time

a

character

is trans

fe

rr

ed

to

the Receiver Holding Register. This

signal

OR'ed

with

OE

is

output

at

Tenn.

15.

3

FRAMING

ERROR (FE):

When

se

t hi·

gh

, this bit indicates that the rece

iv

ed character

has

no

valid

stop

bit, i.e

.,

the

bit

following the parity bit

(if

programmed) is

not

a

high-l

eve

l voltage.

Th

is bit

is

updated each time

a character is transferred

to

the

Rec

eiv

er Holding Register. This si

gnal

is

also

avail

able at Term.

14.

4

EX

T

ER

NALSTATUS(ES):

This

bit

is set

high

by a l

ow.

level

input at Tenn. 38 (ES).

13

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