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2) Memory mapper (MMR) SP6102R-001 signal description
MZ3500
Pin No.
10
12
Polarity
Signal Name
ST
DO
07
A15
A13
IN/OUT
IN
IN/OUT
IN
Function
Main CPU DRAM output buffer (LS244) switching strap.
Bidirectional main CPU data bus.
(Data bus 0 7)
Main CPU address bus.
Used in the memory mapping logic of the MMR for address output for the DRAM, ROM, and
shared RAM. (Address bus 13 ~ 15)
13
A1 IN
Main CPU address bus.
Used in the I/O port select logic of the MMR to assign device number
14
SRES
OUT
Sub-CPU bus request signal.
• After power on: Halts the sub-CPU.
• After write command (LDA-80H: OUT#FD) by the main CPU- Starts the sub-CPU.
This signal is issued after transfer of the main CPU program contained m the ROM-IPL.
(Sub CPU Reset)
15
SRQ
OUT
Sub-CPU bus request signal.
• After power on: Resets bus request to sub-CPU.
• After write command (LDA-02H: OUT#FC) by the main CPU: Place bus request to the sub-CPU
This signal is issued to bus of the sub-CPU, after the main CPU writes to the shared RAM a command
parameter to the sub-CPU or reads the message status from the sub-CPU.
(Sob CPU Request)
16
18
AR13
AR15
OUT
Address signal to the main CPU dynamic RAM.
The main CPU addresssignals.A13-A 15, merged in the memory mapping logic circuit to produce
AR13-AR15. This is means by which the 4 basic and CP/M memory maps are made, along with MSI
and MSO.
19 R32 OUT
BASIC interpreter 32KB mask ROM chip select signal.
Valid when SD2 is active (Sharp ROM based BASIC). Command ILDA 02H OUT 3F D)
(ROM 32K select)
20
21
lOAB
SRDY
IN
Internal MMR I/O port select logic signal.
Goes low by the command IN/OUT #FC-#FF.
(Input/Output Address)
IN
Input of ready signal from the sub-CPU.
(Sub CPU Ready)
22 ROPB
OUT
Chip select signal issued from the main CPU to the 8KB mask ROM.
Valid with SDO active (initialize state).
(ROM ipl)
23
26
ROAB
RODB
OUT
Chip select signal for four chip BASIC interpreter 8KB EPROM (A. B, C, D).
Valid with SD2 active (Sharp ROM based BASIC).
•R32B (alternate choice with the 32KB mask ROM chip select signal).
(ROM A~D Buffer)
27
30
31
RSAB
RSDB
OUT
Row address select signal for the main CPU dynamic RAM (block A-block D).
RAS (ROW ADDRESS SELECT; LINE ADDRESS SELECT) SIGNAL
(Row address Select)
SACK
IN
Input of bus acknowledge signal from the sub-CPU.
When the mam CPU must write a command in the shared RAM a bus request is issued first, then the
command is written in the shared RAM after acknowledgement from the sub-CPU
I At the end of the command cycle bus request is released and the sub CPU executes the command
20-
- SERVICE MANUAL 1
- 1. SPECIFICATIONS 2
- Keyboard layout 3
- 1-3. MZ-1U02 3
- 1-4. MZ-IR03 4
- 1-6. MZ-1R06 5
- 1-7. MZ-1D07 6
- 2-1. SDO (INITIALIZE STATE) 8
- MAIN CPU 8
- M* )S V 1 M/} 9
- MZS.'tOO 10
- 2.3. SD2 (ROM based BASIC) 11
- Operational description 12
- 3. CPU AND MEMORY 13
- L© 'MTR ! 14
- 3-3. Sub CPU and I/O port 15
- 1) Block diagram 16
- ‘ VK IN MEMCKT MM I Mf 20
- 4. CRT DISPLAY 22
- X 25 lines screen.) 24
- For Model 3200 senes 26
- 4-2. Video RAM 27
- 5) Synchronize signal timing 30
- X : Y - 1 : 2 30
- X : Y : 1 : 1 31
- 'iBK byte 32
- (option I) 32
- 48K byte 32
- (option tl) 32
- M Z 3500 34
- CSP 2 Block Diagram 37
- 20 GND IN 38
- ASCII C.G. Structure 40
- 4 9. VSYNC 41
- ARIO = HI 42
- > FIFO Empty? 44
- [Explanation] 45
- Straight line drawing 46
- Whereas 46
- 5. MFD INTERFACE 47
- ^ 0 ^ 0 1 49
- 8) Data write procedure 50
- 5^. FDC (UPD765) 52
- UPD765 signal description 53
- 5-5. Data recording method 54
- <ITE DATA 55
- Write pulse [] fl d fl R 56
- Polarity inversion 56
- +5V RtAD DATA 57
- M -- 3.1 58
- ©"T 58
- Advanced 59
- Does not trace i l^is 59
- 5-11. Media format 60
- (Bbyles) 61
- 02 0\ FF FF 62
- ( 2KX 152 = 304K ) 63
- Stop bit 64
- 6-4. System switch functions 65
- 6-5. 8251AC controls 65
- 2) Data output control 66
- 3) Data input control 67
- 7-D0C># 68
- 3iil>CPU of Ni^ 70
- <i> 71
- 7 4. Data transfer timing 72
- 7-6. I/O port map 73
- 8. OTHER INTERFACES 74
- -<3 ri> 75
- MZ,"500 76
- DIP SW(A) 79
- 1. BLOCK DIAGRAM 80
- A. +5V and +12V supplies 80
- M 7,3500 81
- 3. Alarm circuit 82
- DESCRIPTION 83
- 10-2. Key search timing 84
- JLJl_JlJT_ri_rLJl 85
- Power ON 86
- START (5mS) 86
- 11. SELF CHECK FUNCTIONS 87
- CD SDO bank alternation error 88
- 11-2. Sub-CPU side 89
- .8 test the 90
- 20 lines 90
- /<.y ^ Jf -y > K W 91
- 8) ROM-IPL 92
- S3Si-54Kl=-.*- • 93
- 12. IPL FLOW CHART 96
- MAIN CPU IPL FLOW CHART 2/2 97
- 12 2. SUB CPU IPL FLOW CHART 98
- ■ I I Y Y TV 99
- IjJliJlJjljJljJLllLljLLJ 99
- LlJ LiJ LiJ Lei LiJ LLl LiJ 99
- LJLeJ'LDliJLiJLLjLJLiJ 99
- Pi co vO co fO Pi 100
- Ч Г ^n UO 100
- ¿. ^ О 101
- Û. CM Û 101
- GUIDE LIST 102
- I'l Exteriors 103
- 1 Exteriors 104
- PWB & Fixing angles 105
- [3 Connector 106
- [4] Others 107
- 5 CPU PWB 107
- 5I CPU PWB 108
- U Power supply unit 108
- [6j Power supply unit 109
- П MZ1R06 (RAM board) 111
- SHARP CORPORATION 116
- Industrial Instruments Group 116
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