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YASKAWA PC• 2
1 7
2 YASKAWA PC • 2
Available PLC
CP9200SH
Memobus port
on a CPU module
MP920
MP930
CP217IF
PLC Link Unit
Wiring Diagram
(refer to P2-53)
RS-232C [Wiring Diagram 1]
RS-422 [Wiring Diagram 4]
RS-422 [Wiring Diagram 3]
RS-232C [Wiring Diagram 1]
[Wiring Diagram 2]
RS-232C [Wiring Diagram 1]
217IF
ZM-71SE
Model Setting
CP9200SH
/MP900
19200bps
Even
8
1
CRC (fixed)
Baud Rate
Parity
Transmission
Code
Data Length
Stop Bit 1
Port
Error Check
Item Setting of PLC
19200bps
Even
1
Comm. Parameter of ZM-**
0 (fixed)
Port Delay Timer
1
8
Communication Setting
The recommended communication parameter setting of both PLC and ZM-** is as follows:
Available Memory
Memory Bit Write TYPE Remarks
MW (holding register) 0
IW (input register) 1
MB (coil) 4
IB (input relay) 6
Set the memory to the extent of the memory range of each PC model. In case of using the [Bit Write] memory as the
bit device of the [Output Action] is [Momentary W], the other bits will be cleared when the bit memory is output,
because the [Bit Write] will be output by one word (refer to P5-10, reference 14-7 of ZM-71SE Instruction Manual).
Use [TYPE] number to assign indirect memory for macro programs.
Available: Unavailable:
When setting the MB/IB memories, set the bit No. by HEX.
MBxxxxx
DEC
Bit No. : HEX
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