Sharp VL-DC1E Manual de Instruções descarregar pdf (Página 263)

100

101

74xx

 National Instruments Corporation 6-89 Multisim Component Reference Guide

outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the

input does not affect the state of the flip-flops.

6.4.15574xx823 (9-Bit D-type Flip-Flop)

This device consists of nine D-type edge-triggered flip-flops. It has 3-STATE true outputs and

is organized in broadside pinning. The buffered Clock (CP) and buffered Output Enable (OE

)

are common to all flip-flops. The flip-flops will store the state of their individual D inputs that

meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE

LOW the contents of the flip-flops are available at the outputs. When the OE

is HIGH, the

outputs go to the high impedance state. Operation of the OE

input does not affect the state of

the flip-flops. In addition to the Clock and Output Enable pins, the 74F823 has Clear (CLR

)

and Clock Enable (EN

) pins. When the CLR is LOW and the OE is LOW, the outputs are

LOW. When CLR

is HIGH, data can be entered into the flip-flops. When EN is LOW, data on

the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN

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